The present invention pertains to the operation of a processor or the like. More particularly, the present invention pertains to resolving instruction starvation for a thread in a multi-threaded processor.
As is known in the art, a processor includes a variety of sub-modules, each adapted to carry out specific tasks. In one known processor, these sub-modules include the following: an instruction cache, an instruction fetch unit for fetching appropriate instructions from the instruction cache; decode logic that decodes the instruction into a final or intermediate format, microoperation logic that converts intermediate instructions into a final format for execution; and an execution unit that executes final format instructions (either from the decode logic in some examples or from the microoperation logic in others). As used herein final format instructions are referred to as microoperations.
Programming code to be executed by the processor can sometimes be broken down into smaller components referred to as “threads.” A thread is a series of instructions whose execution achieves a given task. For example, in a video phone application, the processor may be called upon to execute code to handle video image data as well as audio data. There may be separate code sequences whose execution is designed to handle each of these data types. Thus, a first thread may include instructions for video image data processing and a second thread may be instructions for audio data processing. Stated another way, a thread is a self contained program that is usually associated with a thread identifier and during execution in a multi-threaded environment its architectural state can be maintained while executing instructions from another thread.
In most processors, threads are processed by a processor in succession. In general, it is accepted practice that the execution of decoded microoperations should take precedence over the fetching of new, undecoded instructions. This is because, it is more likely that the decoded microoperations will be appropriately executed, while newly, fetched instructions may eventually be “killed” as a result of a branch misprediction, for example. Starting the instruction fetch after execution of these microoperations however, is not always masked, resulting in some period of delay waiting for decoded instructions to refill the execution pipeline. Thus, the execution of instructions for one thread can be negatively impacted
The use of multi-threaded processors has been suggested in the art. In such a processor, it may switch between execution of two or more threads. In other multi-threaded processors, the threads may be executed simultaneously. In either of these processors, there may be no delineation between how the threads are treated. In particular, code from one thread is given the same priority as code from another thread. This could lead to a negative impact on overall system performance, especially when execution of critical code is suspended or slowed by the execution of non-critical code. The accepted practice of giving preference to the execution of microoperations over the fetching of new instructions could have an increased negative impact in a multithreaded processor, especially if the decoded microoperations are for a first thread and the instructions to be fetched are for a second thread that is to be processed simultaneously (or in parallel) with the first thread. There may exist a situation where the processing of the first thread either blocks or unduly delays instruction fetching for the second thread. For the second thread, this can be referred to as instruction side (Iside) starvation.
In view of the above, there is a need to detect and resolve instruction starvation in a multi-threaded processor.